Integrated circuit memory systems that utilize non-volatile memory devices in combination with random access memory devices may support a data dumping operation that occurs in response to a read instruction received at an interface of the memory system. In a conventional data dumping operation, a page of data stored in a non-volatile memory device may be initially transferred over a bus to a random access memory before subsequent transfer from the random access memory to an interface (e.g., host interface) of the memory system. This dumping operation, which typically takes many clock cycles to complete, may involve data transfer between a non-volatile memory device and a random access memory device that are integrated within a common semiconductor substrate.
FIG. 1 illustrates a conventional memory system 100 having a plurality of interconnected memory devices therein. In particular, the memory system 100 is illustrated as including a host interface 141, a read-only memory (ROM) 144, a random access memory (RAM) 145 and a non-volatile memory device 120. This non-volatile memory device 120, which may be a flash memory device, may be communicatively coupled by an interface unit (FI) 142 to the system bus 146. A processing unit 143 (a/k/a processor) is also provided to control operation of the components of the memory system 100. This processing unit 143 is communicatively coupled by the system bus 146 to the other components of the memory system 100.
As illustrated by the dotted lines (1) and (2) shown in FIG. 1, a request for non-volatile memory data, which may be issued by a host processor (not shown) and received at the host interface 141, may result in a first transfer of non-volatile memory data (e.g., page of data) from the non-volatile memory device 120 to the random access memory device 145, via the system bus 146. A second data transfer operation may then be performed, under control of the processing unit 143, to transfer the data to the host interface 141. Alternatively, if the original request for non-volatile memory data is issued by the processing unit 143, then the second data transfer operation may include transferring data from the random access memory device 145 to the processing unit 143, as illustrated by dotted line (3).
As will be understood by those skilled in the art, the timing delays associated with the data transfer paths ((1) and (2) or (1) and (3)) illustrated by FIG. 1 may increase as the page capacity of the non-volatile memory device 120 is increased. This increase in delay may result in an unacceptably long latency between the time a read instruction is received at the host interface 141 and the time the “read” data is first made available to the system bus 146 for transfer to the host interface 141.